In recent years, integrated circuits have been realized that can provide essentially all circuit functions of a desired system on one chip. Such an integrated circuit has been referred to as a “System On a Chip” (SOC) or system large scale integrated circuit “System LSI”. As semiconductor manufacturing process have enabled the scaling down of circuit features, there has been a jump in the number gates integrated on a system LSI, as well as an increase in the throughput (e.g., processing capability/speed) of a system LSI.
A system LSI can be used in a number of applications including but not limited to image processing, encryption/decryption processing, filtering and/or encoding/decoding processes. Of course, such applications can include various types of input/output signals, processing algorithms, and timing requirements. Increasingly, system LSIs can provide more complicated processing with faster processing times. For this reason, recent system LSIs are increasingly being employed for signal processing applications.
FIG. 6 shows a conventional design flow for a system LSI with a software/hardware cooperative design system. The flow of FIG. 6 shows a cooperative design system that includes an algorithm description 1. An algorithm description 1 can represent a system LSI design in the form of a high level language, such as a general purpose program language like C, as but one example. An algorithm description 1 may also be in the form of a dedicated operation level description language that can be converted into a lower level description, such as a register transfer level (RTL) description 7. As is well understood, an RTL description 7 may be realized into hardware with hardware resources having a memory unit, such as a register, and an execution processing unit such as an adder.
All the functions of a system LSI are described in the form of an operation description in the algorithm description 1. It is known that a processing speed for a system LSI can be related to the proportion of the design realized in hardware versus the proportion realized in software. That is, if a greater part of a system LSI is realized as hardware, a processing speed can be faster. However, such an approach can limit the flexibility of a resulting device, as it can be difficult to change functionality after the device is manufactured. In addition, realizing a greater part of a system LSI in hardware can result in a larger overall device, thus manufacturing costs can be higher. On the other hand, if a greater part of a system LSI is realized as software, then changing the functionality of the device may be easier, and a resulting device can be smaller. However, software can be inherently slower than hardware, so a resulting device may have reduced processing speed as compared to one in which a greater part of the system LSI is realized as hardware.
Referring still to FIG. 6, due to the above constraints, a conventional software/hardware cooperative design system may divide system LSI functions into those realized as hardware and those realized as software (step S201). Such a division of functions may be based on predetermined considerations such as circuit scale (e.g., size), processing time, and cost.
If hardware resources are designed from the start (e.g., from “scratch”), development cost may be too high, and development time may be too long. For this reason, hardware components may be in the form of hardware “macros” composed of hardware intellectual property (IP). Such hardware IP can be accumulated as reusable design components, which can represent IP of excellent quality and in wide use that may be readily incorporated into a system LSI structure.
In the arrangement of FIG. 6, hardware can be designed on the basis of a basic instruction processor 11, such as a microprocessor for carrying out general purpose arithmetic operations, and a dedicated instruction processor 12 for executing particular processing according to a given application, such as the processing of an input/output signal. In general, a designed processor in hardware IP form can be used as a basic instruction processor 11. Thus, a basic instruction processor 11 can be a design in RTL form created by a group specializing in processor design, which may be different from a group which designs a system LSI. Such basic instruction processor 11 can be provided with a description for simulation 8a. 
If a basic instruction processor 11 is decided upon, a process may continue with a design of a dedicated instruction processor 12. A dedicated instruction processor 12, like a basic instruction processor 11, may be designed on the basis of an RTL design. Alternatively, a dedicated instruction processor 12 may be designed using an behavior synthesis. In an behavior synthesis design, functions of a dedicated instruction processor 12 can be described in the form of a high level language (step S202). From such a high level representation, an behavior synthesis (step S203) can obtain a dedicated instruction processor RTL description 7b and a description of such a process for simulation 8b. 
Once a dedicated instruction processor RTL description 7b is obtained, such a description can be checked to determine if the dedicated instruction processor 12 can be formed within predetermined circuit scale (e.g., size) restrictions (step S204). If a predetermined circuit scale will be exceeded (NG), a process can return to step S201, to repeat the system LSI design steps. On the other hand, if such a check indicates circuit scale is satisfactory (OK), an RTL description of a system LSI can be formed that includes a basic instruction processor RTL description 7a and dedicated instruction processor RTL description 7b connected to one another by a bus portion RTL description 7c (step S205). It is understood that a basic instruction processor RTL description 7a and dedicated instruction processor RTL description 7b, as shown by items 11 and 12 can be designed to connect to one another through a predetermined bus interface.
Next, in the software design, an application program 9 and a device driver 17 may be described with a high level language (step S206). A device driver 17 may be for driving the dedicated instruction processor 12 and basic instruction processor 11. An application program 9 and device driver 17 are converted into a machine language instruction set 10 by an assembler and/or compiled by a compiler (step S207).
The operation of a system LSI design may then be simulated. In particular, descriptions for simulation of a dedicated instruction processor 8b, basic instruction processor 8a, and bus portion 8c can be brought together in a coupling description for simulation 8. A coupling description for simulation 8 and machine language instruction set 10 can then be subject to an instruction simulation. In this way, a simulation for a software design can be carried out under the same environment as a system LSI structure (step S208).
In an instruction set simulator, hardware and software are simulated to ensure that the design of the software and hardware has no errors. Step S208 may also include measuring a time (e.g., speed) performance and power consumption characteristics of a system LSI during actual use. These performance results can be checked to see whether they meet predetermined criteria (step S209). If a result of such a check indicates the criteria are not met (NG), a process can return to a step S201 to re-execute a division of functions. On the other hand, if a result of such a check indicates the criteria are met (OK), the design of the system LSI is complete. Thereafter, a basic instruction processor RTL description 7a, dedicated instruction processor RTL description 7b, and bus portion RTL description 7c are logically composed to form actual gate structures for the system LSI.
FIG. 7 shows a configuration of a processor portion of a system LSI that can be obtained according to the above mentioned conventional method of design. The conventional processor portion is shown in a block diagram, and includes a basic instruction processor 11, a dedicated instruction processor 12, an interprocessor communication bus 13, and a system controlling unit 15. The basic instruction processor 11 can include a power supply controlling unit 41, a clock generating unit 42, a program counter 43, a conditional flag 44, an instruction fetch register 45, and an instruction decoder 46. In a similar fashion, the dedicated instruction processor 12 can include a power supply controlling unit 51, a clock generating unit 52, a program counter 53, a conditional flag 54, an instruction fetch register 55, and an instruction decoder 56.
The basic instruction processor 11 and dedicated instruction processor 12 transmit and receive data to and from each other through the interprocessor communication bus 13. The system control unit 15 supplies a power supply and basic clock signal to the basic instruction processor 11 and dedicated instruction processor 12.
In the basic instruction processor 11, a power supply controlling unit 41 can receive a power supply input from the system control unit 15. The power supply controlling unit 41 can supply or not supply the power supply to internal circuits of the basic instruction processor 11 according to an ON-OFF control. The clock generating unit 42 can generate a clock signal of a predetermined frequency according to a basic clock signal input from the system control unit 15. The clock signal of the clock generating unit 42 can be provided internal circuits of the basic instruction processor 11. Program counter 43 specifies the address when an instruction fetch register 45 reads out an instruction. Instruction fetch register 45 reads out an instruction from a storage device, such as a program memory (not shown), and stores such an instruction for decoding and execution. The instruction decoder 46 refers to the instruction fetch register 45 and decodes the fetched instruction to thereby execute the instruction.
As noted above, portions of the dedicated instruction processor 12 have the same configuration as those of the basic instruction processor.
The dedicated instruction processor 12 executes processing when necessary. Thus, when dedicated instruction processor 12 functions are not needed, the dedicated instruction processor 12 can enter a standby mode of reduced power consumption. To enter a standby mode, the instruction decoder 46 of the basic instruction processor 11 refers to the instruction fetch register 45 and decodes the fetched instruction to thereby execute the instruction. Such an instruction indicates that a power supply and clock signal for the dedicated instruction processor 12 are to be stopped. And the basic instruction processor 11 transmits a command to the dedicated instruction processor 12 through interprocessor communication bus 13. In response to such a command, the instruction decoder 56 of the dedicated instruction processor 12 refers to the instruction fetch register 55 and decodes a fetched instruction to thereby execute the instruction corresponding to the command. The dedicated instruction processor 12 stops the supply of the power supply from power supply controlling unit 51 to internal circuits of the dedicated instruction processor 12, and stops the supply of a clock signal from clock generating unit 52 to internal circuits of the dedicated instruction processor 12. In this way, the dedicated instruction processor 12 can be placed into the standby mode.
A dedicated instruction processor 12 can proceed from a standby mode to an activation mode, in which a dedicated instruction processor 12 can process data. To proceed to the activation mode, a basic instruction processor 11 can transmit a command that indicates a change to the activation mode to the dedicated instruction processor by way of interprocessor communication bus 13. The dedicated instruction processor 12 will then control the second power supply controlling unit 51 and the second clock generating unit 52 in a bootstrap fashion such as an interrupt to enable the operation mode to proceed to the activation mode.
In a conventional system LSI like that described above, upon the input of a command from basic instruction processor 11, dedicated instruction processor 12 can control power supply controlling unit 51 and clock generating unit 52 to place the operation mode to either the activation mode or standby mode. Thus, in such an arrangement, basic instruction processor 11 monitors the operation state of the dedicated instruction processor 12 in order to determine whether the dedicated instruction processor 12 should be maintained in one mode (e.g., standby or activation), or switched to another mode (e.g., activation or standby). In response to such information, the basic instruction processor 11 issues the command.
A drawback to such a conventional arrangement is that it takes the good amount of time that passes between the reception of the command to enter the standby mode and the actual point at which the standby mode is achieved. In particular, a certain amount of time is required for the basic instruction processor 11 and the dedicated instruction processor 12 to decode the instruction corresponding to such the command and control corresponding circuits to place them in the standby mode, and is required for the basic instruction processor 11 transmits the command to the dedicated instruction processor 12 through interprocessor communication bus 13. During such a time period, electric power must be consumed.
One particular application where such a drawback is a concern is mobile type terminals. In recent mobile type terminals, requests to control a power supply occurs frequently, as preserving battery life is an important feature. It follows that in such applications where power supplies a controlled frequently (e.g., modes are switched to and from a standby mode frequently), electric power consumed during such mode switching times cannot be ignored. Accordingly, there is a need to arrive at some way of shortening the time required to control a power supply.
In addition, if additional time is required to control a power supply, accurate control of a power supply may not be possible, and presents an obstacle to further increasing the high speed operation of a system LSI.
Furthermore, it is necessary for the system LSI is designed that the basic instruction processor 11 and the dedicated instruction processor 12 are designed with the upper level description. A drawback to such a conventional method of designing is that it doesn't take account for that. It is difficult to use the way of the both processor designed with the upper level description.
In light of the above, there is a need to provide a system LSI in which power supply management, or the like, of a dedicated instruction processor can be carried out at a higher speed than conventional approaches. In particular, it would be desirable to provide a system LSI in which a basic instruction processor can readily obtain the state of a dedicated instruction processor, and issue a command thereto for power supply management. It would also be desirable to provide a method for designing such a system LSI and provide a program for the same on a machine readable recording medium.